[ih] Intel 4004 vs the IMP and other ancient history

[John Levine]

It appears that Brian E Carpenter via Internet-history <brian.e.carpenter at gmail.com> said:
>As late as 1973, I believe you still had to go up the Digital
>range as far as a PDP-11/45 to get multiple levels of interrupt

No, the original 11/20 had a four-level priority interrupt, numbered
BR4 to BR7 plus a higher priority NPR (non-processor request) to do DMA.
The 11/45 added levels BR1 through 3.

>On 16-Nov-21 11:54, Jack Haverty via Internet-history wrote:
>> True for more modern systems, but in the era of the 316/516, inexpensive
>> computers sometimes did I/O in the simplest possible manner.  E.g., to
>> handle I/O on a serial interface, the CPU might have to take an
>> interrupt on every byte, read that byte from the hardware interface, and
>> re-enable the interface quickly enough for it to be ready to handle the
>> next byte, ...
>> 
>> That's how a PDP-8/I I worked with in 1968 worked. ...

Depends on how much you wanted to pay.  The PDP-8 and 8/I had single cycle
data break where the device provided the data address and transferred a
word in or out of memory, and the slower but cheaper three-cycle data break
where the device provided a fixed address (programmed with diodes I think)
of two words which were the word count and data address that the CPU updated,
did the transfer, and then told the device if the count incremented to zero.

Logic was expensive in those days so if you could get by with an interrupt per
character or word you did.  The disk, drum, and DECtape controllers used data break,
but the 680 multiline teletype controller had a one bit buffer per line so the
computer had to scan characters in and out one bit at a time.  It was only 110 baud,
but still.

R's,
John

PS: I still have the crumbling paper manuals for both.