[ih] Intel 4004 vs the IMP

[Noel Chiappa]

    > E.g. a register-register MOV took 1.7 microseconds, but a memory-memory
    > move .. seems to have taken 1.7+4.9=6.6 usec, so about 1/5th of a MIP

Ooops, I mistakenly was in the -11/23 timing appendix, not the -11/03; the
latter was considerably slower: 3.5 usec basic, 2.5(sic)+9.1=11.6 usec.
(Indirect was even slower.) So about 1/10th of a MIP.


    > From: Jack Haverty

    > E.g., to handle I/O on a serial interface, the CPU might have to take
    > an interrupt on every byte
    > ...
    > I think that kind of issue is the one Alex referred to about selecting
    > the 316 because of its interrupt mechanism. ... how the hardware
    > handled I/O on all those interfaces was a crucial factor in selecting
    > the 516.

Yes and no. The IMP's modem and host interfaces were both DMA (in the sense
that the CPU only got a single interrupt - which diverted instruction
processing in the CPU to other instructions - for every packet, not on every
word; the details differed significantly from modern DMA, though - see
below). But there was a timing issue.

Per 'The interface message processor for the ARPA computer network',
available here:

  https://www.walden-family.com/public/1970-imp-afips.pdf

"To send a packet, the IMP program sets up memory pointers to the packet and
then activates the interface ... The interface takes successive words from
the memory using its assigned output data channel and transmits them
bit-serially (to the Host or to the modem). When the memory buffer has thus
been emptied, the interface notifies the program via an interrupt".

The details are intetesting: the IMP used "a set of 16 multiplexed channels
(which implement a 4-cycle data break)". This is through a device called the
DMC, the 'Direct Multiplex Control' (sometimes 'Data Multiplex Control').
Notice the "4-cycle data break"; consulting the DMC manual (also online),
this was very similar to the '3-cycle data break' used on many early DEC
machines, up through the PDP-8. This kept the buffer address and count in
main memory (to reduce to cost of devices); the downside is that it increased
the memory bandwidth usage. (The 4 cycles were 1) current buffer address
read, ii) buffer extent read, iii) data read/write, iv) modified buffer
address write-back.)

(Hey, it could have been worse; the DM11 asynchronous line interface of the
early PDP-11 kept the _shift registers_ in main memory, and used DMA to gain
access to them during input/output. At least it was efficient DMA - the
memory address was stored in the device! :-)

The timing issue comes from the fact that, as far as I can tell from
the IMP hardware manual:

  https://walden-family.com/impcode/imp-hardware.pdf

there was _no_ buffering on the modem and host interfaces, just the shift
register; not so bad on the host interface, which used a handshake, and could
be paused, but potentially problematic on the synchronous modem interface;
after a word arrived, it had to be written to memory before the first _bit_
of the next word arrived. (The DM11 had the same issue.)


    > That's why I suggested that the I/O capabilities of a microprocessor
    > needed to be considered when trying to figure out how it compared to
    > the 516, more so than just classic metrics like raw memory and CPU speed.

That part I agree with. (But don't forget the address space, either; the
4004 really had too small an address space to be usable as a router at _any
point in time_.)

	Noel