[ih] BBN C-series computers

[Paul Ruizendaal]

This is the internet history list, not the computer architecture history list, so I’d like to close this thread with a brief summary of on and off list responses.


The MBB processor:

The MBB processor is documented in this paper (available from the ACM library, unfortunately behind a paywall):
M. F. Kraley, R. D. Rettberg, P. Herman, R. D. Bressler, and A. Lake, “Design of a User-Microprogrammable Building Block” in Proceedings of the 13th Annual Microprogramming Workshop, IEEE, New York, 1980.
It is an interesting read and I can certainly recommend it; it also discusses some aspects of the C/30 and C/70 configurations.

The MBB processor seems to have been word (not byte) addressable, with 20 bit addresses and data paths. It is highly reminiscent of the Alto, with I/O device controllers partially implemented in microcode. It is also somewhat reminiscent of the TI990 and the later Sparc in that it had 1024 registers with a visible window of 16 registers. It is unique in that the processor had two optional daughter boards to customise the system: (i) a board to assist with macro-instruction decoding, (ii) an MMU board.

The C/30 version seems to have had a macro-instruction daughter board, but with addresses going straight through. When used as an IMP, some 30% of microcycles seem to have gone on I/O processing and the remaining 70% on executing H316 code.

The C/70 version had both daughter boards. The MMU board divided the 1MW address space into 128 pages of 4KW, and had protection & dirty bits per page. It could hold page tables for up to 8 tasks. 128 pages by 4KW is only 19 bits, perhaps the MMU board used 1 bit to simulate byte accesses. Apparently, there was also a ‘switch’ version of the C/70, without the MMU board and running a minimal OS (but using the “C” microcode & board).

The C/70 seems to have implemented a load/store type architecture with 40 basic instructions, each offering one of 19 addressing modes in an orthogonal setup. The 19 addressing modes were designed around typical C data access operations. Next to that there were 44 specialised instructions.

Procedure calls were very fast, as specialised instructions existed to switch to a new register bank as part of the call, with spilling to main memory upon deep recursion. Apparently it was possible for C code to ‘call' into microcode, and this may be how system calls were done.

According to the paper mentioned above, it is all documented in detail in the "MBB Microprogrammer's Handbook" BBN Report No. 4268, Feb. 1980. Unfortunately, this document does not seem to be available on the DTIC website.


BBN-UNIX for the C/70:

This was a port of the V7 based Unix that BBN had running on the PDP11, with various BSD-type extensions. It had the Gurwitz TCP/IP stack integrated, and accessible via the Gurwitz API (which was compatible with the earlier NCP Unix API). I would guess that some of the earlier IPC features (Haverty’s await() and capac() calls, shared memory areas) were also available.

I’m highly intrigued by this, as some of my own experiments in the past year have been along similar lines (but on 16 bit hardware).